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AS1536/as1537 12-bit, single supply, low-power, 73ksps a/d con- verters datasheet www.austriamicrosystems.com revision 1.01 2 - 22 1 general description the AS1536/as1537 are low-power, 12-bit, 73ksps ana- log-to-digital (a/d) converters specifically designed for single-supply a/d applications. superior ac characteris- tics, very low power consumption, and robust packaging make these ultra-small devices perfect for battery-pow- ered analog-data collection devices. the integrated successive-approximation register (sar) and a fast (1.5s) sampling track/hold time provide an economic and highly-reliable a/d conversion solution. the AS1536/as1537 operate from a single 2.7v to 5.25v supply. the as1537 requires an external refer- ence, using less power than the AS1536, however, the AS1536 features an internal 2.5v reference. as with the as1537, the AS1536 can also be used with an external reference, which uses the input range 0v to v ref , including the positive supply range. the as1537 consumes only 3mw (v dd = 3v) at the 73ksps maximum sampling spe ed. both devices feature a low-current (0.3a) shutdown mode, which reduces power consumption at slower throughput rates. data accesses are made via the standard, high-speed 3-wire serial interface, which is spi-, qspi-, and microwire-compatible. both devices contain an internal clock, however, both devices also support an external clock for increased flexibility. the AS1536/as1537 are available in an 8-pin soic-150 package. figure 1. block diagram 2 key features 12-bit resolution with 7.5s conversion time sampling rate: 73ksps straight binary (u nipolar) data format single-supply operation:+2.7v to +5.25v internal 2.5v reference (AS1536) low power-consumption: - 4mw (73ksps, AS1536) - 3mw (73ksps, as1537) - 66w (1ksps, as1537) - 1w (shutdown mode) integrated track/hold amplifier internal clock spi/qspi/microwire 3-wi re serial interface operating temperature range: -40 to +85oc 8-pin soic-150 package 3 applications the devices are ideal for remote sensors, data-acquisi- tion, data logging devices, lab instruments, or for any other space-limited a/d devices with low power con- sumption and single-supply requirements. AS1536/as1537 control logic output shift register internal clock 12-bit sar track/ hold 2.5v ref AS1536 only 12-bit sar 6 dout 5 gnd 1 vdd 7 csn 8 sclk 3 shdnn 2 ain 4 ref
www.austriamicrosystems.com revision 1.01 3 - 22 AS1536/as1537 datasheet - table of content contents 1 general description ......................................................................................................... .................... 2 2 key features ................................................................................................................ ........................ 2 3 applications ................................................................................................................ .......................... 2 4 pinout ...................................................................................................................... ............................. 4 pin description ................................................................................................................ ..................................... 4 5 absolute maximum ratings .. .................................................................................................. ............. 5 6 electrical characteristics .................................................................................................. .................... 6 timing characteristics ............... .......................................................................................... ................................ 8 7 typical operating characteristics ................ ........................................................................... ............. 9 8 detailed description ........................................................................................................ ................... 12 analog input ................................................................................................................... .................................... 12 track/hold ..................................................................................................................... ..................................... 13 external clock ................................................................................................................. ................................... 13 timing and control .......... .............. .............. .............. .............. ........... ........... ........... .......... ................................ 13 transfer function .............................................................................................................. ................................. 15 reducing supply current ........................................................................................................ ........................... 15 internal 2.5v reference (AS1536) ............................................................................................... ...................... 16 external reference ............................................................................................................. ............................... 16 9 application information ..................................................................................................... ................. 17 initialization ........................ ......................................................................................... ....................................... 17 serial interface ............................................................................................................... .................................... 17 layout considerations .......................................................................................................... ............................. 19 10 package drawings and markings .............................................................................................. ...... 20 11 ordering information ...................................................................................................... ................. 21
www.austriamicrosystems.com revision 1.01 4 - 22 AS1536/as1537 datasheet - pinout 4 pinout figure 2. pin assignments (top view) pin description table 1. pin descriptions pin number pin name description 1vdd positive supply voltage . +2.7v to +5.25v 2ain sampling analog input . 0v to v ref range. 3 shdnn three-level shutdown input . pulling this pin low puts the AS1536/as1537 in shutdown mode, down to 4a (max) supply current. the devices are fully operational with this pin high or floating. note: for the AS1536, pulling this pin high enables the internal reference; let- ting this pin float disables the intern al reference allowing for the use of an external reference. see also pin 4. 4ref a/d conversion reference voltage . this pin serves as the internal 2.5v reference output for the AS1536; bypass this pin with a 4.7f capacitor. this pin also serves as the external re ference voltage input for the as1537, or for AS1536 if the internal reference is disabled. bypass this pin with a minimum of 0.1f when using an external reference. see also pin 3. 5gnd analog and digital ground 6dout serial data output . data changes state at sclk?s falling edge. note: this pin is high-impedance when pin csn is high. 7csn active-low chip select . the falling edge of this pin initiates a conversion. note: when this pin is high, dout is high-impedance. 8sclk serial clock input . this pin clocks data out at rates up to 2.1mhz. AS1536/ as1537 4 ref 3 shdnn 2 ain 1 vdd 5gnd 6dout 7csn 8sclk
www.austriamicrosystems.com revision 1.01 5 - 22 AS1536/as1537 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the de vice at these or any other cond itions beyond those indicated in section 6 electrical characteristics on page 6 is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments vdd to gnd 0.3 +7 v ain to gnd -0.3 v dd + 0.3v v ref to gnd -0.3 v dd + 0.3v v digital inputs to gnd -0.3 v dd + 0.3v v dout to gnd -0.3 v dd + 0.3v v dout current -25 +25 ma continuous power dissipation (t amb = +70oc) 471 mw derate 5.88mw/oc above +70oc operating temperature range -40 +85 oc storage temperature range -60 +150 oc package-body peak temperature 260 c the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020d ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices? .
www.austriamicrosystems.com revision 1.01 6 - 22 AS1536/as1537 datasheet - electrical characteristics 6 electrical characteristics v dd = +2.7v to +5.25v, 73ksps, f sclk = 2.1mhz (50% duty cycle ); AS1536:4.7f capacitor at ref, as1537: external reference; v ref = 2.5v applied to ref; t amb = t min to t max (unless otherwise specified). table 3. electrical characteristics symbol parameter conditions min typ max units dc accuracy 1 resolution 12 bits relative accuracy 2 1 lsb dnl differential non-linearity no mi ssing codes over temperature 1 lsb offset error 6 lsb gain error 3 6 lsb gain temperature coefficient 1 ppm/c dynamic specifications (10khz sine-wave input, 0v to 2.5vp-p, 73ksps, f sclk =2.1mhz) sinad signal-to-noise + distortion ratio 67 70.5 db thd total harmonic distortion up to the 5th harmonic -83 -80 db sfdr spurious-free dynamic range 80 88 db small-signal bandwidth -3db rolloff 2.5 mhz full-power bandwidth 2.5 mhz conversion rate t conv conversion time 5.5 7.5 s t acq track/hold acquisition time 1.5 s throughput rate 4 f sclk = 2.1mhz 73 ksps t ap aperture delay figure 27 on page 14 7ns aperture jitter <50 ps analog input input voltage range 0 v ref v input capacitance 21 pf internal reference (AS1536 only) ref output voltage t amb = +25oc 5 2.47 2.50 2.53 v ref short-circuit current 45 ma ref temperature coefficient AS1536 30 ppm/c load regulation 6 0 to 0.2ma output load 0.35 mv c refbyp capacitive bypass at ref 4.7 f external reference (v ref = 2.5v) input voltage range 1.00 v dd + 50mv v input current 100 150 a input resistance 18 25 k ref input current in shutdown shdnn = 0v 0.01 10 a c refbyp capacitive bypass at ref 0.1 f
www.austriamicrosystems.com revision 1.01 7 - 22 AS1536/as1537 datasheet - electrical characteristics digital inputs : sclk, shdnn, csn v ih sclk, csn input high voltage 0.7x v dd v v il sclk, csn input low voltage 0.3x v dd v v hyst sclk, csn input hysteresis 0.2 v i in sclk, csn input leakage v in = 0v or v dd 0.01 1 a c in sclk, csn input capacitance 7 15 pf v sh shdnn input high voltage v dd - 0.4 v v sl shdnn input low voltage 0.4 v shdnn input current shdnn = 0v or v dd 4.0 a v sm shdnn input mid voltage 1.1 v dd - 1.1 v v flt shdnn voltage, floating shdnn = float v dd /2 v shdnn max allowed leakage, mid input shdnn = float 50 na digital output : dout v ol output voltage low i sink = 5ma 0.4 v i sink = 16ma 0.8 v oh output voltage high i source = 0.5ma v dd - 0.5 v i l tri-state leakage current csn = v dd 0.01 10 a c out tri-state output capacitance csn = v dd 7 15 pf power requirements v dd supply voltage 2.7 5.25 v i dd supply current int. reference (AS1536), v dd = 3.6v 1.4 2.0 ma int. reference (AS1536), v dd = 5.25v 1.6 2.3 external reference, v dd = 3.6v 1.0 1.4 external reference, v dd = 5.25v 1.2 1.7 shutdown mode, v dd = 3.6v 0.3 2 a shutdown mode, v dd = 5.25v 0.6 4 psr power-supply rejection 8 v dd = v ddmin to v ddmax , full-scale input 1 mv 1. tested at v dd = +2.7v. 2. relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. 3. offset nulled. 4. achievable with standard timing (see figure 25 on page 14) . 5. sample tested at 0.1% aql. 6. external load should not change during conversion for specified accuracy. 7. guaranteed by design; not s ubject to production testing. 8. measured as [v fs (v ddmin ) - v fs (v ddmax )] with external reference. table 3. electrical characteristics (continued) symbol parameter conditions min typ max units
www.austriamicrosystems.com revision 1.01 8 - 22 AS1536/as1537 datasheet - electrical characteristics timing characteristics v dd = +2.7 to +5.25v, t amb = t min to t max (unless otherwise specified). figure 3. dout enable-time load circuits figure 4. dout disable-time load circuits table 4. timing characteristics parameter symbol conditions min typ max units acquisition time 1 1. to guarantee acquisition time, t acq is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired t acq 1.5 s sclk falling-to-dout valid t do figure 3 , c load = 50pf 20 200 ns csn falling-to-output enable t dv figure 3 , c load = 50pf 240 ns csn rising-to-output disable t tr figure 4 , c load = 50pf 240 ns sclk clock frequency f sclk 0 2.1 mhz sclk pulse width high t ch 200 ns sclk pulse width low t cl 200 ns sclk low-to-csn falling setup time t cs0 50 ns dout rising-to-sclk rising 2 2. guaranteed by design; not s ubject to production testing. t str 0 ns csn pulse width t cs 240 ns c load 50pf c load 50pf 6k gnd dgnd dout dout high-impedance to v oh and v ol to v oh +2.7v high-impedance to v ol and v oh to v ol 6k dgnd 6k c load 50pf c load 50pf 6k dgnd gnd dgnd dout dout v oh to high-impedance +2.7v v ol to high-impedance
www.austriamicrosystems.com revision 1.01 9 - 22 AS1536/as1537 datasheet - typical operating characteristics 7 typical operating characteristics v dd = 3.0v, v ref = 2.5v, f sclk = 2.1mhz, c load = 50pf, t amb = +25oc (unless otherwise specified). figure 5. integral nonlinearity vs. digital output code fi gure 6. differential nonlinea rity vs. digital output code figure 7. fft @ 1khz figure 8. fft @ 10khz figure 9. enob vs. v ref figure 10. enob vs. input signal frequency -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 digital output code inl (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 digital output code dnl (lsb) . -160 -140 -120 -100 -80 -60 -40 -20 0 0 5 10 15 20 25 30 35 40 input signal frequency (khz) fft (dbc) . -160 -140 -120 -100 -80 -60 -40 -20 0 0 5 10 15 20 25 30 35 40 input signal frequency (khz) fft (dbc) . fsample = 75ksps n fft = 16384 fsample = 75ksps n fft = 16384 11.05 11.15 11.25 11.35 11.45 11.55 11.65 11.75 1.3 2.3 3.3 4.3 5.3 reference voltage (v) enob (bit) . 11.42 11.47 11.52 11.57 11.62 010203040 frequency (khz) enob (bit) .
www.austriamicrosystems.co m revision 1.01 10 - 22 AS1536/as1537 datasheet - typical operating characteristics figure 11. supply current vs. supply voltage figure 12. supply current vs. temperature figure 13. shutdown supply current vs. supply voltage figure 14. shutdown supply current vs. temperature figure 15. offset error vs. supply voltage fi gure 16. offset voltage vs. temperature 0 0.5 1 1.5 2 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 supply voltage (v) supply current (ma) . 0 0.5 1 1.5 2 -40 -15 10 35 60 85 temperature (c) supply current (ma) . internal reference external reference internal reference external reference 0 0.5 1 1.5 2 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 supply voltage (v) shutdown supply current (a) . 0 0.5 1 1.5 2 -40 -15 10 35 60 85 temperature (c) supply current (a) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 supply voltage (v) offset error (lsb) . 0.4 0.6 0.8 1 1.2 -40 -15 10 35 60 85 temperature (c) offset error (lsb) .
www.austriamicrosystems.co m revision 1.01 11 - 22 AS1536/as1537 datasheet - typical operating characteristics figure 17. gain error vs. supply voltage figure 18. gain error vs. temperature figure 19. internal reference voltage vs. supply voltage figure 20. internal reference voltage vs. temperature figure 21. integral nonlinearity vs. supply voltage fi gure 22. integral nonlinearity vs. temperature -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 supply voltage (v) gain error (lsb) . -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 -40 -15 10 35 60 85 temperature (c) gain error (lsb) . 2.49 2.495 2.5 2.505 2.51 2.73.13.53.94.34.75.15.5 supply voltage (v) internal reference voltage (v) . 2.48 2.49 2.5 2.51 2.52 -40 -15 10 35 60 85 temperature (c) internal reference voltage (v) . 0.4 0.45 0.5 0.55 0.6 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 supply voltage (v) inl (lsb) . 0 0.1 0.2 0.3 0.4 0.5 -40 -15 10 35 60 85 temperature (c) inl (lsb) .
www.austriamicrosystems.co m revision 1.01 12 - 22 AS1536/as1537 datasheet - detailed description 8 detailed description the AS1536/as1537 analog-to-digital converters have two modes of operation: normal a/d conversion mode ? pulling pin shdnn high or leaving it open puts the device into normal a/d conver- sion mode. shutdown mode ? pulling pin shdnn low shuts the device down and reduces supply current below 2a (v dd 3.6v). note: pulling pin csn low starts a conversion. the conversion re sult is available at pin dout in unipolar serial for- mat (see timing and control on page 13) . figure 23 shows a basic configuration for th e AS1536/as1537. the integrated input track/hold circuitry and a succes- sive-approximation register (sar) circui try convert analog input signals to a digital 12-bit output. no external-hold capacitor is needed for the track/hold circuit. the devices convert analog input signals in the 0v to v ref range in 13.7s (includes tr ack/hold acquisition time). the AS1536 internal reference is trimmed to 2.5v; the as1 537 requires an external reference. both devices can accept external reference voltages from 1.0v to v dd . the serial interface requires only three digital lines (at pins sclk, csn, and dout) and provides a simple microprocessor interface. figure 23. operational diagram analog input figure 24 illustrates the integrated comparator sampling architecture. the full scale input voltage is set by the voltage at pin ref. figure 24. equivalent input circuit AS1536/ as1537 +2.7v to +5.25v AS1536 ? 4.7f as1537 ? 0.1f reference input required for as1537, optional for AS1536 0.1f 4.7f + 6 dout 5 gnd 1 vdd 7 csn 8 sclk 3 shdnn 2 ain 4 ref + ? + comparator r in c switch 14pf c hold 13pf ? ref ain + c hold 13pf ? sample switch c switch includes all parasitics gnd s&h and dac
www.austriamicrosystems.co m revision 1.01 13 - 22 AS1536/as1537 datasheet - detailed description the devices? input tracking circuitry has a 2.5mhz small-signa l bandwidth, thus it is possible to under-sample (digitize high-speed transient events) and measure periodic signals with bandwidths exceeding the devices? sampling rate. note: anti-aliasing filtering should be used to avoid aliasing of unwanted high-frequency signa ls into the bandwidth of interest. input protection internal protection diodes clamp the analog input to v dd and gnd, allowing the input to swing from (gnd - 0.3v) to (v dd + 0.3v) without damage. however, for accurate conv ersions near full scale, the input must not exceed v dd by more than 50mv, or be lower than gnd by 50mv. note: if the analog input exceeds the supply by 50mv, limit the input current to 2ma. track/hold in track mode, the analog signal is acquired and stored in th e internal hold capacitors. during acquisition, the analog input at pin ain charges capacitor c hold (see figure 24 on page 12) . bringing csn low ends the acquisition interval and the charge on c hold represent the sampled input voltage. in hold mode, the t/h switches are opened thus the input is disconnected from the capacitor c hold. during this mode the successive approximation is performed which in turn forms a digital representat ion of the analog input signal. at the end of the conversion, the input side of the in meantime discharged c hold switches back to ain, and c hold charges to the input signal again. the maximum time for the t/h to acquire a signal (t acq ) is a function of how quickly its input capacitance is charged. t acq increases proportionally to the input signal?s impedance, and at higher impedances more time must be allowed between conversions. t acq is also the minimum time needed for the signal to be acquired, and is calculated by: t acq = 10(r s + r in ) x 21pf (eq 1) where: r in = 4.5k r s = the input signal?s source impedance. t acq is never less than 1.5s. source impedances < 1k do not significantly affect t he ac performance of the devices. note: higher source impedances can be used if a 0.01f capaci tor is connected to the analog input. note that the input capacitor forms an rc filter with the input source impedance, limiting the devices? input signal bandwidth. external clock the AS1536/as1537 do not require an external clock for anal og-to-digital data conversion. this allows the micropro- cessor to read back the conversion results at any clock rate from up to 2.1mhz at any time. the clock duty cycle is unrestricted if each clock phase is at least 200ns. note: the external clock must not be run while a conversion is in progress. timing and control conversion-start and data-read operations are controll ed by digital inputs csn and sclk. refer to figures 25 - 27 (see page 14 ) for graphical timing and control information. the falling edge on pin csn initiates a conversion sequence: 1. the t/h stage holds the voltage at pin ain, and the a/d conversion begins. 2. pin dout changes from high-impedance to logic-lo w. sclk must be kept low during the conversion. 3. the internal sar stores the data during the conversion process. 4. pin dout going high indicates the conversion process has completed. 5. the rising edge of pin dout can be used as a framing signal. 6. sclk shifts the data out of this register any time after the conversion is complete. 7. dout transitions on the falling edge of pin sclk. 8. the next falling clock edge produces the msb of the c onversion at dout, followed by the remaining bits. since there are 12 data bits and one leading high-bit 13 falling cl ock edges are needed to shift out these bits, respectively.
www.austriamicrosystems.co m revision 1.01 14 - 22 AS1536/as1537 datasheet - detailed description 9. extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of csn, produce trailing zeros at dout and have no effect on the conversion process. 10. for minimum cycle time, clock out t he data with 12.5 clock cycles at full sp eed using the rising edge of dout as the eoc signal. pull csn high after reading the conv ersion?s lsb. after the specified minimum time (t cs ) csn can be pulled low to initiate the next conversion. figure 25. serial interface standard cycle timing diagram figure 26. serial interface minimum cycle timing diagram figure 27. detailed serial interface timing diagram csn sclk dout conversion in progress hold eoc track/hold stage track clock out serial data track cycle time tota l = 13 . 7 s trailing 0s idle 0.24s t cs 0s t conv 7.5s hold interface idle b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0s 12.5 x 0.476s = 5.95s hold track/hold stage track track hold total = 13.7s cycle time dout b9 b8 b7 b6 b5 b4 b3 b0 b1 csn eoc clock out serial data idle interface idle 0.24s t cs 7.5s t conv 0s 12.5 x 0.476s = 5.95s sclk b2 conversion in progress b11 b10 track/acquire csn sclk dout internal track/hold t conv t ap t dv t str hold t cso t do t ch t cl t cs t tr track/acquire b2 b1 b0
www.austriamicrosystems.co m revision 1.01 15 - 22 AS1536/as1537 datasheet - detailed description transfer function the data output from the AS1536/ as1537 is binary (unipolar), and figure 28 depicts the nominal transfer function. code transitions occur midway between successive integer lsb values. note: if v ref = +2.50v, then 1 lsb = 610v (2.50v/4096). figure 28. unipolar transfer function reducing supply current power consumption can be reduced significantly by powering down the devices between conversions. figure 30 shows a plot of an average supply current versus sampling rate. wake-up time (t wake ) can also factor into r educed power consumption. t wake is defined as the time from when pin shdnn is deasserted to the time when a conversion may be initiated (see figure 29) . figure 29. shutdown sequence timing diagram for the AS1536 using the internal reference, t wake depends on the time in shutdown mode (see figure 31) since the external 4.7f reference bypass capacitor slowly loses charge during shutdown. the wakeup time for AS1536 and as1537 using an internal reference are largely dependent on the external reference?s power-up time. the wakeup time for the adc itself from shutdown mode is approximately 4s. 11...111 11...1110 11....101 00...011 00...010 00...001 00...000 output code 0123 input voltage ain fs - 3/2lsb full scale (fs) transition full scale = v ref zero scale = 0 1lsb = v ref /4096 complete conversion sequence conversion 0 conversion 1 power-up shutdown t wake power-up csn shdnn dout
www.austriamicrosystems.co m revision 1.01 16 - 22 AS1536/as1537 datasheet - detailed description figure 30. supply current vs. sampling rate figure 31. powerup time vs. time in shutdown internal 2.5v reference (AS1536) the AS1536 internal 2.5v reference output is connec ted to pin ref and also drives the internal dac (see figure 24 on page 12) . ref output can be used as a reference voltage source for other components and can source up to 400a. the internal reference is enabled by pulling pin shdnn high. letting shdnn float disables the internal reference, which allows the use of an external reference (see external reference on page 16) . pin ref should be bypassed with a 4.7f capacitor as shown in figure 23 on page 12 . larger capacitors increase wake-up time when the devices exit shutdown mode (see layout considerations on page 19) external reference both devices can operate with an external reference at pin re f. the external reference should be within the +1.0v to v dd voltage range to achieve specified accuracy. the minimum input impedance is 18k for dc currents. note: to use an external reference with the AS1536, disable the internal re ference by letting pin shdnn float. during conversion, the external reference should be capabl e of delivering up to 250a of dc load current and have an output impedance 10 . the recommended minimum value for the bypass capacitor is 0.1f. if the reference has higher output impedance or is noisy, bypass it close to pin ref with a 4.7f capacitor. 0 100 200 300 400 500 600 700 800 0.001 0.01 0.1 1 10 time in shutdown (s) power-up delay (s) . 0.1 1 10 100 1000 10000 0.1 10 1000 100000 sampling rate (sps) supply current (a) . internal reference external reference 3v 5v 5v 3v internal reference
www.austriamicrosystems.co m revision 1.01 17 - 22 AS1536/as1537 datasheet - application information 9 application information initialization when power is first applied, and if shdnn is not pulled lo w, it takes the fully discharged 4.7f reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. with an external reference, the initialization time is 10s after the power supplies have stabilized. note: a/d conversions must not be started dur ing initialization of the AS1536/as1537. serial interface the AS1536/as1537 fully support spi, qspi, and microwire inte rfaces. for spi, select the correct clock polarity and sampling edge in the spi control registers (set cpol = 0 and cpha = 0). microwire, spi, and qspi all transmit a by te and receive a byte at the same time. serial interface configuration the AS1536/as1537 serial interface can be configured with the following procedure: 1. put the microprocessor?s serial interface into ma ster mode (so that it generates the serial clock). 2. select a clock frequency up to 2.1mhz. 3. keeping sclk low, pull csn low via one of the microprocessor?s general-purpose i/o lines. 4. monitor dout for its rising edge to determine the eoc, or wait the maximum conversion time specified before acti- vating sclk. 5. activate sclk for a minimum of 11 clock cycles. t he first falling clock edge produces the msb of the conversion. output data transitions on the falling edge of sclk, and is available in msb-first format at pin dout. observe the sclk to dout valid timing characteristic. data can be cl ocked into the microprocessor on the rising edge of sclk. 6. csn should be pulled high at or after the 13th falli ng clock edge. if csn remains low, trailing zeros are clocked out after the lsb. 7. with csn = high, wait the minimum specified time, t cs , before initiating a new conversion by pulling csn low. if a conversion is aborted by pulling csn high before the conv ersion?s end, wait for the minimum acquisition time, t acq , before starting a new conversion. note: csn must be held low until all data bits are clocked out. 8. data can be output in two bytes or continuously (see figure 34 on page 18) . the bytes contain the result of the con- version padded with one leading 1, two sub-bits, and trailing 0s. spi and microwire interfaces when interfacing the AS1536/as1537 to a microprocessor?s spi or microwire interface (see figure 32 and figure 33 ), set spi control registers cpol = 0 and cpha = 0. figure 32. spi serial interface connections AS1536/ as1537 cpu ssm miso i/o sck 6 dout 7 csn 8 sclk
www.austriamicrosystems.co m revision 1.01 18 - 22 AS1536/as1537 datasheet - application information figure 33. microwire serial interface connections a conversion process begins on the falling edge of csn (see figure 34) . dout goes low, indicating a conversion is in progress. wait until dout goes high or until the maximu m specified conversion time elapses before starting another conversion. two consecutive 1-byte reads are required to retrieve th e full 12 bits from the devices. output data transitions occurs on the fall ing edge of sclk, and is clocked into the microprocessor on the rising edge of sclk. the first byte contains a leading 1, and seven bits of conversion result data. the second byte contains the remaining five bits of conversion re sult data, and three trailing zeros. figure 34. spi/microwire serial interface timing (cpol = cpha = 0) qspi when interfacing the AS1536/as1537 to a microprocessor?s qspi interface (see figure 35) , set qspi control register cpol = cpha = 0. figure 35. qspi serial interface connections AS1536/ as1537 cpu si i/o sk 6 dout 7 csn 8 sclk 1st byte read 2nd byte read lsb msb eoc t conv csn sclk dout d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 high-z when csn is high AS1536/ as1537 cpu ssm miso csm sck 6 dout 7 csn 8 sclk
www.austriamicrosystems.co m revision 1.01 19 - 22 AS1536/as1537 datasheet - application information unlike the spi interface, which requires two 1-byte reads to acquire the 12 da ta bits from the AS1536/as1537, qspi allows the minimum number of clock cycle s necessary to clock in the data. the devices require 13 clock cycles from the microprocessor to clock out the 12 data bits with no trailing zeros (see figure 36) . note: the maximum clock frequency to ensure compatibility with qspi is 2.097mhz. figure 36. qspi serial interface timing (cpol = cpha = 0) layout considerations the AS1536/as1537 require proper layout and design procedures for optimum performance. use printed circuit boards; wirewrap boards should not be used. separate analog and digital traces from each other. analog and digital traces should not run parallel to each other (especially clock traces). digital traces should not run beneath the AS1536/as1537. use a single-point analog ground at g nd, separate from the digital ground (see figure 37) . connect all other ana- log grounds and dgnd to this star ground point for further noise reduction. no other digital system ground should be connected to this single-point analog ground. the ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply may affect the AS1536/as1537 high-speed comparator. bypass this supply to the single-point analog ground with 0.1f and 4.7f bypass capacitors (see figure 37) . the bypass capacitors should be placed as close to the device as possible for optimum power supply noise-rejection. if the power supply is very noisy, a 10 resistor can be connected as a low-pass filter to attenuate supply noise. figure 37. recommended ground design sclk csn dout eoc t conv lsb msb d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 high-z when csn is high AS1536/ as1537 power supplies digital circuitry 0.1f + 4.7f 10 (optional) gnd gnd +3v 1 vdd 5 gnd +3v +3v dgnd
www.austriamicrosystems.co m revision 1.01 20 - 22 AS1536/as1537 datasheet - package drawings and markings 10 package drawings and markings figure 38. 8-pin soic-150 package symbol min max a1 0.10 0.25 b 0.36 0.46 c 0.19 0.25 d 4.80 4.98 e 3.81 3.99 e1.27bsc h 5.80 6.20 h 0.25 0.50 l .041 1.27 a 1.52 1.72 0o 8o zd 0.53ref a2 1.37 1.57 notes: 1. lead coplanarity should be 0 to 0.10mm (.004?) max. 2. package surface finishing: (2.1) top: matte (c harmilles #18-30). (2.2) all sides: matte (charmilles #18-30). (2.3) bottom: smooth or matte (charmilles #18-30). 3. all dimensions exclusive of mold flash, and end flash from the pack- age body shall not exceed 0.24mm (0.10?) per side (d). 4. details of pin #1 identifier are optional but must be located within the zone indicated.
www.austriamicrosystems.co m revision 1.01 21 - 22 AS1536/as1537 datasheet - ordering information 11 ordering information the devices are available as the standard products shown in table 5 . all devices are rohs compliant and free of halogene substances. table 5. ordering information part number marking description delivery form package AS1536-bsou AS1536 12-bit, single supply, low-power, 73ksps a/d converters with internal +2.5v reference tubes 8-pin soic-150 AS1536-bsot AS1536 12-bit, single supply, low-power, 73ksps a/d converters with internal +2.5v reference tape and reel 8-pin soic-150 as1537-bsou as1537 12-bit, single supply, low-power, 73ksps a/d converters tubes 8-pin soic-150 as1537-bsot as1537 12-bit, single supply, low-power, 73ksps a/d converters tape and reel 8-pin soic-150
www.austriamicrosystems.co m revision 1.01 22 - 22 AS1536/as1537 datasheet copyrights copyright ? 1997-200 9, austriamicrosystems ag, schloss premstaett en, 8141 unterpremstae tten, austria-europe. trademarks registered ?. all rights reserved. the materi al herein may not be reprodu ced, adapted, merged, trans- lated, stored, or used witho ut the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austria- microsystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a syst em, it is necessary to check with aust riamicrosystems ag for current informa- tion. this product is intended for use in normal commercial applications. applications requiring extend ed temperature range, unusual environmental requirements, or high reliability app lications, such as military, medical life-support or life- sustaining equipment are specifically not recommended wit hout additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the m anufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or ar ising out of the furnishing, performance or use of the tech- nical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag a-8141 schloss premstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors a nd representatives, please visit: http://www.austriamicr osystems.com/contact-us

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